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2019 MME Jack T. Kimbrell Distinguished Lecture

Engineering Teaching Research Laboratory, Pullman, WA
Reception at 10:30 a.m. in ETRL 119 with light refreshments. Lecture begins at 11 a.m. in ETRL 101.
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About the event

Featuring Dr. Gaurang Choksi , Vice-President – Technology Development Director – Assembly & Test Technology Development Core Competencies at Intel Corporation.

See more here.

Heterogeneous Electronic Packaging: Turning Concepts to Reality!

Enabling the Creation, Computing, Communication, and Management of Data

Technology advances in electronic packaging have supported and sustained Moore’s Law silicon scaling, and have evolved to become an important enabler of product performance. Progress in the areas of computing, memory, communications and networking for a wide range of market segments including consumer electronics, high performance cloud computing and emerging areas such as autonomous driving and artificial intelligence will drive the need for increased integration and differentiation. This results in an extremely diverse set of 2-D, 2.5-D and 3-D packaging architectures and designs with multiple levels of integration; requiring novel constructs, materials technologies, modeling and simulation tools, test methods, and manufacturing processes. Rapid progress in the area of heterogeneous packaging and assembly / test will continue to require significant improvements in modeling/simulation software tools and measurement tools/techniques for design, assembly manufacturing and testing, and materials for mechanical integrity, signal integrity, power delivery and thermal requirements. Challenges that need to be addressed for facilitating analysis and characterization to enable efficient design, materials selection and associated assembly and test manufacturing processes will be reviewed. The role of crossfunctional teams, decisions for trade-offs across electrical, thermal and structural integrity performance, and the need for new competencies moving forward, will be discussed.